1. Field of the Invention
The present invention relates to semiconductor devices comprising two or more dies stacked vertically on top of one another, and methods of making the semiconductor devices.
2. Description of the Related Art
Vertical stacking of multiple flip chips in a stacked die package requires wafers to be processed with through silicon interconnects to enable face-to-back (F2B) flip chip bonding. The wafers are typically thinned or back-ground during the process of forming the interconnects, and therefore known processes for stacking the thinned wafers require a support carrier that is temporarily bonded to the wafers during handling and equipment processing to prevent warping. More particularly, the support carrier can improve the rigidity of the thinned wafers in the wafer-level through silicon interconnect fabrication process and wafer-level assembly process. However, the process of bonding the support carrier to the wafer involves additional process and material developments, additional equipment investment, increased packaging cost and additional process steps directed to the bonding of the support carrier to and de-bonding of the support carrier from the wafer. Exemplary known processes for forming the stacked die package will be illustrated with reference to FIGS. 1(a) to 1(d).
FIG. 1(a) shows a known process of forming a thinned wafer that is temporarily bonded to a first support carrier. The process begins with a wafer 1 that is etched at its front surface 1a to form vias 2 therein. The vias 2 extend from the front surface 1a of the wafer 1 and partially into the wafer 1. The front surface 1a of the wafer 1 and the vias 2 are plated with a dielectric layer, a barrier metal layer and a seed layer (collectively referred to as numeral 3). The plated vias 2 are then filled with a metallic material 4 such as copper (Cu) to form through silicon interconnects 5. Thereafter, metallization and passivation layers (collectively referred to as numeral 6) are formed on the front surface 1a of the wafer 1. To prepare the wafer 1 for thinning or back-grinding, a first support carrier 7 is bonded to the front surface 1a of the wafer 1 using a bonding material 7a. The thinning of the wafer 1 occurs at its rear surface 1b, opposite to the front surface 1a. The wafer 1 is back-ground until the through silicon interconnects 5 are exposed at their rear end portions 5a. Metallization and passivation layers (collectively referred as numeral 8) are formed at the rear surface 1b of the thinned wafer 1, followed by forming of under bump metallization (UBM) pads 9. Solder bumps 10 are formed on the under bump metallization pads 9.
FIGS. 1(b)(i) and 1(b)(ii) show a known process of stacking flip chips 11 onto the thinned wafer with UBM pads 9 from FIG. 1(a). To prepare the front surface 1a of the thinned wafer for stacking, a second support carrier 12 is temporarily bonded to the rear surface 1b of the wafer using bonding material 12a followed by removal (de-bonding) of the first support carrier 7 from the front surface 1a. The flip chips 11 are stacked over the front surface 1a of wafer 1 such that solder bumps 13 of the flip chips 11 are aligned with the through silicon interconnects 5 of the wafer 1. The flip chips 11 are then under-filled with a resin 14 and the second support carrier 12 removed. Solder bumps 15 are then provided on the rear surface 1b of the wafer 1. The wafer 1 with flip chips 11 stacked thereon is singulated into individual units 16 which are mounted onto a substrate 17. The assembly is over-molded with molding material 18 and mounted with solder balls 19 before being singulated into individual packages.
FIGS. 1(c)(i) and 1(c)(ii) show an alternate known process of stacking flip chips 11 onto the thinned wafer 1 with UBM pads 9 and solder bumps 10 from FIG. 1(a). The first support carrier 7 is removed from the thinned wafer 1. The wafer 1 is singulated into individual dies which are mounted onto a substrate 17. Flip chips 11 are stacked on the front surface of the dies such that solder bumps 13 of the flip chips 11 are aligned with the through silicon interconnects 5 of the dies. The flip chips 11 are then under-filled with resin 14 and the entire assembly over-molded with molding material 18. Solder balls 19 are formed on the underside of the substrate 17 followed by singulation into individual packages.
FIG. 1(d) shows a semiconductor package resulting from the processes described by FIGS. 1(a) and 1(b), or 1(a) and 1(c).
The known processes of forming the stacked die package involve the use of one or more support carriers which can result in the disadvantages as highlighted above. There is therefore a need to provide a process that can at least reduce usage or avoid the use of the support carriers.